In Application-Specific Integrated Circuit (ASIC) technology fields for manufacturing integrated circuits using submicron technologies, a logic circuit designer uses a large number of logic cells, which play a dominant role in the design of microchips. When logic cells are used, a circuit designer selects suitable logic cells to be used in a target circuit from a specific list of logic cells, namely a standard cell library. All logic cells listed in such a standard cell library must be operated in a specified manner, and a circuit designer assumes that all of the logic cells will precisely operate in the intended way.
Therefore, the providers of the standard cell library must verify the functions of each logic cell. Various attempts to verify such functions are continuously made.
However, a unified test method, which is universally applicable to various design rules and various standard cell libraries, is in great demand.